Method and controller for processing data multiplication in RAID system

ABSTRACT

The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 32 bits or 64 bits). One or several XOR operation units form a multiplication unit of a data sector. When computing on-line, data in a disk drive of a disk array are performed with XOR operations in accordance with one of the map tables using an XOR operation unit as one unit while computing on the multiplication unit to obtain a product of multiplication. 
     Making use of the RAID system established according to the disclosed method, only XOR operations are required to compute parity data or recover damaged user data. Moreover, several calculations can be performed simultaneously. Therefore, the efficiency of the RAID system can be effectively improved.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a Divisional application of U.S. patent application Ser. No. 11/513,385, filed on Aug. 31, 2006, which claims the benefit of provisional Application No. 60/596,142, filed on Sep. 2, 2005, the entirety of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of Invention

The invention relates to a method and controller for processing data multiplication in a RAID system and, in particular, to a method and controller for processing simultaneously a large amount of data multiplication operations in a RAID system.

Related Art

The redundant array of independent disk (RAID) is a disk subsystem designed to enhance access efficiency, to provide better fault-tolerance ability, or both. The RAID utilizes a disk striping technique to enhance the access efficiency. Data are stored separately according to bytes or groups of bytes in many different disk drives, so that the read/write I/O requests can be performed in parallel on many disk drives. On the other hand, a mirroring technique or a disk striping technique with distributive parity data is used to provide the fault-tolerance ability.

The ability of fault tolerance is related to the number of parity data sets stored in the RAID system. Taking RAID5 as an example, it is designed to store an extra set of parity data in addition to the user data. The parity data is usually called the P value, or sometimes the XOR parity because it is the calculation result of XOR operations on the corresponding user data. The formula is: P=D ₀ +D ₁ +D ₂ + . . . +D _(n-1)  (1) where + represents the XOR operation, P represents the parity data series, D₀, D₁, D₂, . . . , D_(n-1) represents the user data series, respectively, and n denotes the number of user data disks. As RAID5 only stores one parity data set, it can only allow one of the user data disks having errors (e.g. damaged or out of order) at a time. The data on the user data disk having errors is recovered using the corresponding P value and the corresponding data on the other normal user data disks by means of the same XOR operations. For example, if D₁ has an error, then D₁ can be recovered as follows: D ₁ =D ₀ +D ₂ + . . . +D _(n-1) +P

-   -   where + also denotes the XOR operation.

Considering the fault tolerance demand on more than one user data disk, some systems are designed to store multiple parities. “Reed-Solomon Codes” are usually adopted to set up this type of RAID systems, which allow more than one disk drive having errors. RAID6 belongs to this category. It has at least two parities to allow two or more disk drives having errors at the same time.

Take the RAID6 system with two parities as an example. The two parities are conventionally called P and Q. The formula for computing P is the same as the one in the RAID5 system. The value of Q is obtained using the following formula. Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . +g ^(n-1) ·D _(n-1)  (2)

If two data disks D_(x), D_(y) are damaged, then a careful derivation gives: D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy))  (3) D _(y)=(P+P _(xy))+D _(x)  (4)

-   -   where A and B are constants only related to x and y:         A=g ^(y-x)·(g ^(y-x)+1)⁻¹  (5)         B=g ^(−x)·(g ^(y-x)+1)⁻¹  (6)     -   and P_(xy) and Q_(xy) are the values of P and Q when both D_(x)         and D_(y) are 0, i.e.,         P _(xy) +D _(x) +D _(y) =P  (7)         Q _(xy) ±g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q  (8)

Aside from the fact that the power “y−x” is a normal subtraction, the other algebraic operations in Eqs. (2) to (8) are all operations following the rules of the Galois Field. Moreover, g is a generator of the Galois Field. It usually be chosen as g=2.

The addition operation in the Galois Field is in fact the XOR operation. Its multiplication operation is related to the field of GF(2^(a)). For the definitions, properties, and operational rules, please refer to (1) “The mathematics of RAID6”, H. Peter Anvin, December, 2004; and (2) “A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like Systems”, James S. Plank, Software-Practice & Experience, 27(9), pp 995-1012, September, 1997. Eqs. (1) to (8) given above can be found in Ref. (1).

Since the Galois Field is a closed field and there always exists an r for an arbitrary number X satisfying X=2^(r), in the prior art looking up table is a typical method to deal with the multiplication operations in the Galois Field (see Ref. (2)). Take GF(2^(a)) as an example. To find the product of any two numbers X and Y, the procedure is as follows:

-   -   1. Look up a log table to find r and s, which satisfies X=2^(r)         and Y=2^(s). Therefore, X·Y=2^(r+s)=2^(t).     -   2. If t≧2^(a)−1, then t=t−(2^(a)−1).     -   3. Look up an inverse log table to obtain the value of 2^(t).

It is seen from Eqs. (2) and (3) that a large amount of multiplication operations of Galois Field are required for computing Q or recovering the damaged D_(x). In particular, it involves the multiplication of a constant with various different numbers. By means of the conventional method of looking up table, the system has to compute byte by byte and each multiplication operation of Galois Field requires 3 times of table looking up, 1 addition (or subtraction), 1 test and 1 modulo operation. Considering that the sizes of current storage media are frequently tens or hundreds of Giga bytes, such calculations are very inefficient and easy to become the bottleneck of the system. Therefore, how to improve and/or simplify and/or speed up the data multiplication operations in the RAID system is an important issue to be solved in the industry.

SUMMARY OF THE INVENTION

It is an objective of the invention to provide an effective algorithm and a controller implementing the algorithm, so that a huge amount of data multiplication operations can be performed simultaneously, thereby improving the efficiency of a RAID system.

In accordance with one feature of the invention, a method for data multiplication operations in a RAID system is provided. The method includes the steps of: generating at least one map table corresponding to at least one value in a field; selecting a length for an XOR operation unit and forming a multiplication unit using a plurality of the XOR operation units; and for the data stored in one disk drive of the RAID, performing at least one XOR operation using the XOR operation unit as one unit while computing on the multiplication unit according to a map table of the at least one map table, and further performing a plurality of the XOR operations to obtain the multiplication result.

In accordance with another feature of the invention, a controller for processing data multiplication operations in the RAID system is provided. The controller includes: a memory for temporarily storing target data provided by a data source; and a central processing circuit that generates at least one map table corresponding to at least one value in a field, performs at least one XOR operation for the target data stored in the memory using the XOR operation unit as one unit while computing on the multiplication unit according to a map table of the at least one map table, and further performs a plurality of the XOR operations to obtain the multiplication result.

In accordance with another feature of the invention, a method for processing data multiplication operations in a RAID system is provided, which is used to compute the product of a number K with a data series X. The method includes the steps of: generating a map table for the number K; selecting a length of an XOR operation unit, and forming a multiplication unit using a plurality of the XOR operation units; dividing the data series X into at least one the multiplication unit; for the multiplication unit and the map table associated with the number K, performing at least one XOR operation using the XOR operation unit as one unit according to the rules in the map table; and performing the multiplication operation in the previous step on all the multiplication units in the data series X. The multiplication result of the number K with the data series X is obtained once all the multiplication operations are done.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the invention will become apparent by reference to the following description and accompanying drawings which are given by way of illustration only, and thus are not limitative of the invention, and wherein:

FIG. 1 is the primary flowchart of the invention;

FIG. 2 is a flowchart of generating map tables according to the invention;

FIG. 3 is a schematic view of sampling data according to the invention;

FIG. 4 is a schematic view of sampling data in the prior art; and

FIG. 5 is a schematic view of an embodiment of the disclosed disk subsystem employing the method of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be apparent from the following detailed description, which proceeds with reference to the accompanying drawings, wherein the same references relate to the same elements.

A feature of the invention is in the appropriate definitions of operational rules for the data in the RAID system in order to speed up the data operations. In practice, the operational rules for the RAID data are commonly taken to be the algebraic rules of the Galois Field. Therefore, the algebraic rules of the Galois Field are used in the following embodiments. One embodiment of the invention is established on the hypothesis of GF(2^(a)) of the Galois Field and its related algebraic rules. As a=8 is a currently-preferred choice in practice, most of the embodiments in this specification assume the domain of the Galois Field to be GF(2⁸). That is, the covered numbers are between 0 and 255. This is because 2⁸ is exactly the amount represented by one byte which is a basic unit of computer memory. The RAID system accordingly established can accommodate up to 255 user data disks, which are sufficient for normal RAID systems. Although the embodiments in this specification assume GF(2⁸), the invention can be applied to other cases with other hypotheses. In other embodiments of the invention, the disclosed technique may be applied in a Galois field domain different from GF(2⁸). Moreover, the invention can also use the operations in other fields or number systems, as long as appropriate operational rules are found in those fields or number systems.

Most of the embodiments described below take a RAID6 system with two parities as the example. However, the invention can be applied to more general cases. Other RAID 6 systems with more than two parities can be implemented with the disclosed method as well. The conventional formulas quoted in the specification are listed as follows. P=D ₀ +D ₁ +D ₂ + . . . +D _(n-1)  (1) Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . +g ^(n-1) ·D _(n-1)  (2) D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy))  (3) D _(y)=(P+P _(xy))+D _(x)  (4) A=g ^(y-x)·(g ^(y-x)+1)⁻¹  (5) B=g ^(−x)·(g ^(y-x)+1)⁻¹  (6) where P and Q are the two parities in the RAID6 system; x and y are the serial numbers of the two data disks with errors; D_(x) and D_(y) are the user data corresponding to the two data disks x and y; A and B are constants only related to x and y; and P_(xy) and Q_(xy) are the values of P and Q when D_(x) and D_(y) are both 0, i.e., P _(xy) +D _(x) +D _(y) =P  (7) Q _(xy) +g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q  (8)

Aside from the fact that the power “y−x” is a normal subtraction, the other algebraic operations in Eqs. (1) to (8) are all operations following the rules of the Galois Field. Moreover, g is a generator of the Galois Field. It usually be chosen as g=2.

Definition of the Map Table

The map table is a key ingredient of the invention. It is defined as follows.

Suppose Y, X, and K are numbers in GF(2^(a)). That is, Y, X, and K are all composed of “a” bits. If y_(i) and x_(i) represents the i-th bits of Y and X, respectively, then the vectors Y and X can be represented by:

$\begin{matrix} {{Y = \begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ \vdots \\ y_{a - 1} \end{bmatrix}},} & {X =} \end{matrix}\begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ \vdots \\ x_{a - 1} \end{bmatrix}$

Let Y=K·X; that is, Y is the multiplication result of K with an arbitrary number X in the Galois Field. Here K is a given constant. Then the map table of K is defined as an a×a matrix M_(K), whose elements m_(i,j) (0<=i, j<=a−1) are 0 or 1 and satisfy:

$\begin{matrix} {Y = {\begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ \vdots \\ y_{a - 1} \end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix} m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,{a - 1}} \\ m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,{a - 1}} \\ m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,{a - 1}} \\ \vdots & \vdots & \vdots & \vdots & \vdots \\ m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},{a - 1}} \end{bmatrix} \cdot \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ \vdots \\ x_{a - 1} \end{bmatrix}}}}} & (9) \end{matrix}$

In other words,

$\begin{matrix} {{{y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{i,j} \cdot x_{j}} \right)}},{{{wherein}\mspace{14mu} 0} \leqq i \leqq {a - 1}}}{where}{{{m_{i,j} \cdot x_{j}} = x_{j}},{{{{if}\mspace{14mu} m_{i,j}} = 1};}}{{{m_{i,j} \cdot x_{j}} = 0},{{{if}\mspace{14mu} m_{i,j}} = 0.}}} & (10) \end{matrix}$

The addition in the above operations is defined as the XOR operation. Since the elements in the matrix M_(K) are either 0 or 1, the computation of y, can be regarded as follows: the data units x_(j) corresponding to m_(i,j)=1 in the i-th row of the matrix M_(K) are selected to do XOR operations.

Generation of the Map Table

The way of generating the map table is closely related to the algebraic rules of the Galois Field. Take GF(2⁸) as an example. Suppose the product of an arbitrary number X and 2 is X□′, then X□′ can be obtained from the following formula (“+” represents an XOR operation):

${{X\;\bullet^{\prime}} = {\begin{bmatrix} x_{0}^{\prime} \\ x_{1}^{\prime} \\ x_{2}^{\prime} \\ x_{3}^{\prime} \\ x_{4}^{\prime} \\ x_{5}^{\prime} \\ x_{6}^{\prime} \\ x_{7}^{\prime} \end{bmatrix} = \begin{bmatrix} x_{7} \\ x_{0} \\ {x_{1} + x_{7}} \\ {x_{2} + x_{7}} \\ {x_{3} + x_{7}} \\ x_{4} \\ x_{5} \\ x_{6} \end{bmatrix}}};{{{where}\mspace{14mu} X} = \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ x_{3} \\ x_{4} \\ x_{5} \\ x_{6} \\ x_{7} \end{bmatrix}}$

Suppose the map table of K is a given matrix M_(K) and the map table of K′=2·K is the matrix M_(K′). Based on the above formula, one can derive the algorithmic rule A for generating M_(K′) from M_(K), shown in Table 1:

TABLE 1 m′_(0,j) = m_(7,j) , 0 <= j <= 7 m′_(1,j) = m_(0,j) , 0 <= j <= 7 m′_(2,j) = m_(1,j) + m_(7,j) , 0 <= j <= 7 m′_(3,j) = m_(2,j) + m_(7,j) , 0 <= j <= 7 m′_(4,j) = m_(3,j) + m_(7,j) , 0 <= j <= 7 m′_(5,j) = m_(4,j) , 0 <= j <= 7 m′_(6,j) = m_(5,j) , 0 <= j <= 7 m′_(7,j) = m_(6,j) , 0 <= j <= 7

One algebraic feature of the Galois Field is as follows. Start from K=1 and multiply K each time by 2. The derived new K values do not repeat until covering all the numbers in the Galois Field. Take GF(2⁸) as an example. Start from K=1 and record it. Multiply K by 2 each time. After 255 times recording, the derived K values will cover all the GF(2⁸) numbers (except for 0).

According to the above-mentioned algebraic properties of the Galois Field and the algorithmic rule A, all map tables corresponding to different K values, i.e., all the matrix M_(K), can be generated. Please refer to FIG. 1. According to an embodiment of the invention, generating the map tables (step 200) is the first key step of the invention and its implementation is described as follows.

With reference to FIG. 2, while beginning to generate the map tables (step 201), the algorithmic rule A for generating the matrix M_(K′) from the matrix M_(K) should be determined first according to the selected Galois Field GF(2^(a)) and its algebraic rules (step 202), where M_(K) denotes the map table of a constant K and M_(K′) denotes the map table of 2·K. When K=0, its map table is defined to be the zero matrix (step 203). When K=1, its map table is defined to be the identity matrix (step 204). The map tables thus generated are stored in the system memory. The K value whose map table is already produced is marked as “completed” (step 205). Afterwards, K starts from K=1 and is multiplied each time by 2 (step 206). The system checks whether the K value is marked as “completed” (step 207). If so, then the procedure is finished (step 209); otherwise, the map table M_(K) of the new K value is generated according to the algorithmic rule A (step 208). The procedure then returns to step 205, marking K as “completed” and generating the next new K value (step 206), and so on. Steps 205˜208 are repeated until K value is repeated and then the procedure is finished (step 209).

A few map tables in GF(2⁸) are listed below for references.

$\begin{matrix} {K = 0} & {K = {2^{0} = 1}} \\ {M_{0} = \begin{bmatrix} 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \end{bmatrix}} & {M_{1} = \begin{bmatrix} 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{bmatrix}} \\ {K = {2^{27} = 12}} & {K = {2^{55} = 160}} \\ {M_{12} = \begin{bmatrix} 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 0 \\ 1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 \\ 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 \\ 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\ 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 \end{bmatrix}} & {M_{160} = \begin{bmatrix} 0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \\ 0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 0 \\ 0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \end{bmatrix}} \end{matrix}$ Application of the Map Table

One advantage of using the map tables for the multiplication operations in the Galois Field is to avoid the operations of shifting digits or looking up the log table/inverse log table. All it needs is the XOR operations.

Take GF(2⁸) as an example. Suppose Y is the product of a constant 20 and an arbitrary number X, i.e., Y=20·X, and the map table associated with 20 (the matrix M₂₀) is given as:

$\begin{matrix} {M_{20} = \begin{bmatrix} 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \end{bmatrix}} & (11) \end{matrix}$

According to the definition,

$\begin{matrix} {Y = {\begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \\ y_{4} \\ y_{5} \\ y_{6} \\ y_{7} \end{bmatrix} = {{\begin{bmatrix} 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \end{bmatrix} \cdot \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ x_{3} \\ x_{4} \\ x_{5} \\ x_{6} \\ x_{7} \end{bmatrix}} = {\quad\begin{bmatrix} {x_{4} + x_{6}} \\ {x_{5} + x_{7}} \\ {x_{0} + x_{4}} \\ {x_{1} + x_{4} + x_{5} + x_{6}} \\ {x_{0} + x_{2} + x_{4} + x_{5} + x_{7}} \\ {x_{1} + x_{3} + x_{5} + x_{6}} \\ {x_{2} + x_{4} + x_{6} + x_{7}} \\ {x_{3} + x_{5} + x_{7}} \end{bmatrix}}}}} & (12) \end{matrix}$

For example, if X=83, then Y=8, as given below:

${\begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ x_{3} \\ x_{4} \\ x_{5} \\ x_{6} \\ x_{7} \end{bmatrix} = \begin{bmatrix} 1 \\ 1 \\ 0 \\ 0 \\ 1 \\ 0 \\ 1 \\ 0 \end{bmatrix}},{\begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \\ y_{4} \\ y_{5} \\ y_{6} \\ y_{7} \end{bmatrix} = {\begin{bmatrix} {x_{4} + x_{6}} \\ {x_{5} + x_{7}} \\ {x_{0} + x_{4}} \\ {x_{1} + x_{4} + x_{5} + x_{6}} \\ {x_{0} + x_{2} + x_{4} + x_{5} + x_{7}} \\ {x_{1} + x_{3} + x_{5} + x_{6}} \\ {x_{2} + x_{4} + x_{6} + x_{7}} \\ {x_{3} + x_{5} + x_{7}} \end{bmatrix} = {\begin{bmatrix} {1 + 1} \\ {0 + 0} \\ {1 + 1} \\ {1 + 1 + 0 + 1} \\ {1 + 0 + 1 + 0 + 0} \\ {1 + 0 + 0 + 1} \\ {0 + 1 + 1 + 0} \\ {0 + 0 + 0} \end{bmatrix} = \begin{bmatrix} 0 \\ 0 \\ 0 \\ 1 \\ 0 \\ 0 \\ 0 \\ 0 \end{bmatrix}}}}$

If the value of Y is computed using the conventional technique by looking up the log table/inverse log table, then Y=20·83=2²⁰⁶·2⁵²=2²⁰⁶⁺⁵²=2²⁵⁸=2²⁵⁸⁻²⁵⁵=2³=8 which is the same as the result computed by the disclosed technique of the invention. Explanation of the Algorithm

The disclosed algorithm of the invention allows the operations of a huge amount of Galois Field multiplication to proceed at the same time, particularly the multiplication operations of a constant with a lot of different numbers. Therefore, it speeds up the operations in a RAID system.

Please refer to FIG. 1. According to one embodiment of the invention, the disclosed method includes three steps. First, the domain of GF(2^(a)) of the Galois Field is determined. The map tables of all values in GF(2^(a)) are produced according to the algebraic rules of the Galois Field and stored in the memory (step 200). Secondly, the XOR operation unit is enlarged to appropriate w bits. Therefore, the multiplication unit is enlarged to be w a bits (step 300). Thirdly, according to the stored map tables and its operational rules, each data sector of w bits in the multiplication unit are selected as an XOR operation unit for the XOR operation when the system computes the multiplication of the Galois Field on-line (step 400). Wherein, the map tables mentioned in the first step can be generated in real time while processing data operations, instead of being all generated right after the system is turned on. However, if all the map tables can be generated right after the system is power on, it will be more convenient for subsequent operations. On the other hand, if the required map tables are too many and not suitable for production and storage at a time, then real-time generation during the operation is another feasible option.

How to generate the map tables (step 200) is already described above.

The technique of how to enlarge the XOR operation unit to w bits (step 300) is described as follows.

According to the definition of the map table, i.e. Eq. (9), y_(i) and x_(i) denote the i-th bit of Y and X, respectively, where Y and X are numbers in GF(2^(a)). It implies that when the map tables are used for conventional operations, the XOR operation unit is 1 bit and the multiplication unit is a number in GF(2^(a)). The disclosed method of the invention enlarges the XOR operation unit to w bits, and thus the multiplication unit is enlarged to w·a bits. Take GF(2⁸) as an example. If setting w=32, then the XOR operation unit has 32 bits according to the invention, and the multiplication unit has 32·8=256 bits=32 bytes, namely, the set of 32 numbers in GF(2⁸).

One of the chief considerations of selecting the length of the XOR operation unit to be w is the system hardware environment. For example, the consideration could be the operation unit of the CPU or dedicated XOR operation unit or the width of the data bus. If the operation unit of the CPU or dedicated XOR operation unit is 32 bits, then w=32 is an appropriate choice. If the operation unit of the CPU or dedicated XOR operation unit is 64 bits, then setting w=64 is suitable. Of course, it does not imply that the choice of w is necessarily limited to be the same as the length of the operation unit of the CPU or dedicated XOR operation unit. Different w values may be used in other embodiments of the invention.

Another factor influencing the value of w is considering that the basic storage unit (a sector) of the disks had better be an integer multiple of the multiplication unit. Take GF(2⁸) as an example. If setting w=20, then the multiplication unit has 20·8=160 bits=20 bytes. The basic storage unit, i.e. a sector, of the disks usually has 512 bytes. Since 512 is not an integer multiple of 20, therefore additional operations have to be performed when the multiplication unit is incomplete.

After determining the value of w, the system can perform online multiplication of the Galois Field according to the map tables (step 400). The multiplication may be performed for computing a parity or lost user data. The operation rule is still following Eq. (9). However, the XOR operation unit is enlarged to an appropriate w bits, and the multiplication unit is enlarged to w·a bits. That is, both y_(i) and x_(i) have w bits, and both Y and X have w·a bits.

In the following, an embodiment is used to explain the disclosed method. If it is the intention to calculate the product of Y=20·X in GF(2⁸). X is a 32-byte data sector. In the hexadecimal number system, X is represented as follows:

$\begin{matrix} {X = \left. {\overset{B_{0}}{\left| 25 \right.}\mspace{14mu} 2a\mspace{14mu} 1b\mspace{14mu} 33\overset{B_{4}}{\left| 52 \right.}\mspace{14mu} 6a\mspace{14mu} 11\mspace{14mu} 90\overset{B_{8}}{\left| 80 \right.}\mspace{14mu} 46\mspace{14mu} 7c\mspace{14mu} a\; b\overset{B_{12}}{\left| {6e} \right.}\mspace{14mu} 21\mspace{14mu} 5b\mspace{14mu} 44} \right|} \\ {\left. {\overset{B_{16}}{\left| {a\; 5} \right.}\mspace{14mu} 42\mspace{14mu} 78\mspace{14mu} 03\overset{B_{20}}{\left| 77 \right.}\mspace{14mu} 25\mspace{14mu} 19\mspace{14mu} 64\overset{B_{24}}{\left| 01 \right.}\mspace{14mu} 92\mspace{14mu} 47\mspace{14mu} 86\overset{B_{28}}{\left| 22 \right.}\mspace{14mu} 55\mspace{14mu} 9a\mspace{14mu} 76} \right|} \end{matrix}$ where the 0-th byte of X is denoted by B₀, the first byte by B₁, the second byte by B₂, and so on, until B₃₁.

According to the disclosed method, the RAID system computes and stores all the map tables when its starts. Therefore, the map table associated with 20 is already given. Suppose the system CPU is 32-bit. Therefore, w is set to be 32. In this case, Y and X are considered to be the data series composed of 8 units, given as:

-   -   Y=y₀ y₁ y₂ y₃ y₄ y₅ y₆ y₇     -   X=x₀ x₁ x₂ x₃ x₄ x₅ x₆ x₇         where y_(i) and x_(i) represent operation units consisting of 32         bits (4 bytes), 0≦i≦7.

$\begin{matrix} {{{Set}\mspace{14mu} X} = \left. {\overset{x_{0}}{\left| {25\mspace{14mu} 2a\mspace{14mu} 1b\mspace{14mu} 33} \right.}\overset{x_{1}}{\left| {52\mspace{14mu} 6a\mspace{14mu} 11\mspace{14mu} 90} \right.}\overset{x_{2}}{\left| {80\mspace{14mu} 46\mspace{14mu} 7c\mspace{14mu} a\; b} \right.}\overset{x_{3}}{\left| {6e\mspace{14mu} 21\mspace{14mu} 5b\mspace{14mu} 44} \right.}} \right|} \\ {\left. {\overset{x_{4}}{\left| {a\; 5\mspace{14mu} 42\mspace{14mu} 78\mspace{14mu} 03} \right.}\overset{x_{5}}{\left| {77\mspace{14mu} 25\mspace{14mu} 19\mspace{14mu} 64} \right.}\overset{x_{6}}{\left| {01\mspace{14mu} 92\mspace{14mu} 47\mspace{14mu} 86} \right.}\overset{x_{7}}{\left| {22\mspace{14mu} 55\mspace{14mu} 9a\mspace{14mu} 76} \right.}} \right|} \end{matrix}$

The map table of the constant 20 is already given in Eq. (11). Using Eqs. (9) and (12), one obtains (in the hexadecimal system): y ₀ =x ₄ +x ₆=(a5 42 78 03)+(01 92 47 86)=(a4 d0 3f 85) y ₁ =x ₅ +x ₇=(77 25 19 64)+(22 55 9a 76)=(55 70 83 12) y ₂ =x ₀ +x ₄=(25 2a 1b 33)+(a5 42 78 03)=(80 68 63 30) y ₃ =x ₁ +x ₄ +x ₅ +x ₆=(52 6a 11 90)+(a5 42 78 03)+(77 25 19 64)+(01 92 47 86)=(81 9f 37 71) y ₄ =x ₀ +x ₂ +x ₄ +x ₅ +x ₇=(25 2a 1b 33)+(80 46 7c ab)+(a5 42 78 03)+(77 25 19 64)+(01 92 47 86)=(55 5e 9c 89) y ₅ +x ₃ +x ₅ +x ₆=(52 6a 11 90)+(6e 21 5b 44)+(77 25 19 64)+(01 92 47 86)=(4a fc 14 36) y ₆ =x ₂ +x ₄ +x ₆ +x ₇=(80 46 7c ab)+(a5 42 78 03)+(01 92 47 86)+(22 55 9a 76)=(06 c3 d9 58) y ₇ =x ₃ +x ₅ +x ₇=(6e 21 5b 44)+(77 25 19 64)+(22 55 9a 76)=(3b 51 d8 56)

Therefore, Y=|a4 d0 3f 85|55 70 83 12|80 68 63 30|81 9f 37 71∥55 5e 9c 89|4a fc 14 36|06 c3 d9 58|3b 51 d8 56|

The above example assumes that the length of X is 32 bytes. If the length of X is greater than 32 bytes, then X is divided into groups each composed of 32 bytes. Each group of 32 byte forms a multiplication unit. Therefore, the product Y can be obtained by repeating the above operations.

Features of the Algorithm

Using the disclosed algorithm of the invention on the RAID system, the obtained parity is different from that obtained in the prior art. However, its effect and the way of application are completely the same as the prior art.

For example, suppose D₀, D₁, and D₂ are three disk drives for storing user data, which are 32-byte data series, shown as follows (expressed in the hexadecimal system):

$\begin{matrix} {D_{0} = \left. {\overset{B_{0}}{\left| {2a} \right.}\mspace{14mu} 16\mspace{14mu} 10\mspace{14mu} 36\overset{B_{4}}{\left| 50 \right.}\mspace{14mu} 14\mspace{14mu} 18\mspace{14mu} 66\overset{B_{8}}{\left| {5\; c} \right.}\mspace{14mu} 01\mspace{14mu} 06\mspace{14mu} 12\overset{B_{12}}{\left| 35 \right.}\mspace{14mu} 7\; e\mspace{14mu} 46\mspace{14mu} 0\; a} \right|} \\ {\left. {\overset{B_{16}}{\left| {1a} \right.}\mspace{20mu} 39\mspace{14mu} 6f\mspace{14mu} 1\overset{B_{20}}{\left. 7 \middle| 59 \right.\mspace{11mu}}\; 75\mspace{14mu} 48\mspace{14mu} 5d\overset{B_{24}}{\left| {2a} \right.}\mspace{14mu} 07\mspace{14mu} 57\mspace{14mu} 39\overset{B_{28}}{\left| {0f} \right.}\mspace{14mu} 30\mspace{14mu} 21\mspace{14mu} 30} \right|} \end{matrix}$ $\begin{matrix} {D_{1} = \left. {\overset{B_{0}}{\left| 19 \right.}\mspace{14mu} 38\mspace{14mu} 25\mspace{14mu} 26\overset{B_{4}}{\left| {0c} \right.}\mspace{14mu} 49\mspace{14mu} 57\mspace{14mu} 51\overset{B_{8}}{\left| {6a} \right.}\mspace{14mu} 35\mspace{14mu} 27\mspace{14mu} 65\overset{B_{12}}{\left| 23 \right.}\mspace{14mu} 09\mspace{14mu} 62\mspace{14mu} 28} \right|} \\ {\left. {\overset{B_{16}}{\left| 58 \right.}\mspace{14mu} 7f\mspace{14mu} 5d\mspace{14mu} 7e\overset{B_{20}}{\left| 12 \right.}\mspace{14mu} 15\mspace{14mu} 5d\mspace{14mu} 7a\overset{B_{24}}{\left| {3d} \right.}\mspace{14mu} 48\mspace{14mu} 4c\mspace{14mu} 6b\overset{B_{28}}{\left| {5b} \right.}\mspace{14mu} 40\mspace{14mu} 74\mspace{14mu} 4c} \right|} \end{matrix}$ $\begin{matrix} {D_{2} = \left. {\overset{B_{0}}{\left| {7c} \right.}\mspace{14mu} 1c\mspace{14mu} 5d\mspace{14mu} 22\overset{B_{4}}{\left| {3d} \right.}\mspace{14mu} 61\mspace{14mu} 7d\mspace{14mu} 3c\overset{B_{8}}{\left| 75 \right.}\mspace{14mu} 2b\mspace{14mu} 3e\mspace{14mu} 70\overset{B_{12}}{\left| 14 \right.}\mspace{14mu} 4e\mspace{14mu} 42\mspace{14mu} 18} \right|} \\ {\left. {\overset{B_{16}}{\left| {6d} \right.}\mspace{14mu} 0d\mspace{14mu} 6e\mspace{14mu} 05\overset{B_{20}}{\left| 31 \right.}\mspace{14mu} 55\mspace{14mu} 78\mspace{14mu} 47\overset{B_{24}}{\left| {3b} \right.}\mspace{14mu} 72\mspace{14mu} 67\mspace{14mu} 70\overset{B_{28}}{\left| {1f} \right.}\mspace{14mu} 0b\mspace{14mu} 14\mspace{14mu} 3e} \right|} \end{matrix}$ where B₀ denotes the 0-th byte, B₁ the first byte, and so on, until B₃₁. The RAID6 system comprising the three user data disk drives requires additional two party data disk drives for storing parities P and Q. According to Eqs. (1) and (2), one obtains: P=D ₀ +D ₁ +D ₂ Q=2⁰ ·D ₀+2¹ ·D ₁+2² ·D ₂

In the prior art, the values of P and Q in GF(2⁸) are computed as follows:

$\begin{matrix} {P = \left. {\overset{B_{0}}{\left| {4f} \right.}\mspace{14mu} 32\mspace{14mu} 68\mspace{14mu} 32\overset{B_{4}}{\left| 61 \right.}\mspace{14mu} 3c\mspace{14mu} 32\mspace{14mu} 0b\overset{B_{8}}{\left| 43 \right.}\mspace{14mu} 1f\mspace{14mu} 1f\mspace{14mu} 07\overset{B_{12}}{\left| 02 \right.}\mspace{14mu} 39\mspace{14mu} 66\mspace{14mu} 3a} \right|} \\ {\left. {\overset{B_{16}}{\left| {2f} \right.}\mspace{14mu} 4b\mspace{14mu} 5c\mspace{14mu} 6c\overset{B_{20}}{\left| {7a} \right.}\mspace{14mu} 35\mspace{14mu} 6d\mspace{14mu} 60\overset{B_{24}}{\left| {2c} \right.}\mspace{14mu} 3d\mspace{14mu} 7c\mspace{14mu} 22\overset{B_{28}}{\left| {4b} \right.}\mspace{14mu} 7b\mspace{14mu} 41\mspace{14mu} 42} \right|} \end{matrix}$ $\begin{matrix} {Q = \left. {\overset{B_{0}}{\left| {f\; 5} \right.}\mspace{14mu} 16\mspace{14mu} 33\mspace{14mu} f\; 2\overset{B_{4}}{\left| {bc} \right.}\mspace{14mu} 1f\mspace{14mu} 5f\mspace{14mu} 34\overset{B_{8}}{\left| 41 \right.}\mspace{14mu} c\; 7\mspace{14mu} b\; 0\mspace{14mu} 05\overset{B_{12}}{\left| 23 \right.}\mspace{14mu} 49\mspace{14mu} 97\mspace{14mu} 3a} \right|} \\ {\left. {\overset{B_{16}}{\left| 03 \right.}\mspace{14mu} f\; 3\mspace{14mu} 70\mspace{14mu}{ff}\overset{B_{20}}{\left| {b\; 9} \right.}\mspace{14mu} 16\mspace{14mu} 0f\mspace{14mu} a\; 8\overset{B_{24}}{\left| {bc} \right.}\mspace{14mu} 42\mspace{14mu} 4e\mspace{14mu} 32\overset{B_{28}}{\left| {c\; 5} \right.}\mspace{14mu} 9c\mspace{14mu} 99\mspace{14mu} 50} \right|} \end{matrix}$

Using the disclosed method of the invention, the P value is unchanged. The value of Q is as follows (assuming w=32):

$\begin{matrix} {Q = \left. {\overset{B_{0}}{\left| {4a} \right.}\mspace{14mu} 24\mspace{14mu} 03\mspace{14mu} 0a\overset{B_{4}}{\left| 56 \right.}\mspace{14mu} 27\mspace{14mu} 29\mspace{14mu} 7e\overset{B_{8}}{\left| {4c} \right.}\mspace{14mu} 66\mspace{14mu} 1f\mspace{14mu} 5d\overset{B_{12}}{\left| {1d} \right.}\mspace{14mu} 13\mspace{14mu} 1b\mspace{14mu} 51} \right|} \\ {\left. {\overset{B_{16}}{\left| 33 \right.}\mspace{14mu} 22\mspace{14mu} 34\mspace{14mu} 4d\overset{B_{20}}{\left| {0a} \right.\mspace{14mu}}4f\mspace{14mu} 43\mspace{14mu} 05\overset{B_{24}}{\left| 55 \right.}\mspace{14mu} 1f\mspace{14mu} 64\mspace{14mu} 46\overset{B_{28}}{\left| 03 \right.}\mspace{14mu} 2d\mspace{14mu} 15\mspace{14mu} 1c} \right|} \end{matrix}$

Suppose the data in D₀ and D₂ are damaged, they can be recovered by using D₁, P, and Q. Using Eqs. (3), (4), (5), (6), (7), and (8), one obtains: x=0,y=2,A=166,B=167; D ₀=166·P+167·Q+245·D ₁ D ₂ =P+D ₁ +D ₀  (13)

1. In the prior art, each byte is computed one by one to solve: 166·P=|fe 9a d2 9a|2d 30 9a ae|05 be be 55|51 34 78 c3∥75 5c bb 70|31 cf d6 8b|82 96 c2 28|5c 97 54 a3 167·Q=|31 57 0f 63|75 a1 13 5d|15 99 82 01|ad 44 89 f9∥f4 c4 49 33|74 57 03 71|75 e1 16a8|ca 2c 2d 10| 245·D ₁ =|e5 db cd cf|08 85 91 95|4c 26 3a 46|c9 0e b7 30∥9b a1 9d 54|1c ed 9d a7|dd 70 83 b9|99 8b 58 83| Therefore, D ₀=|2a 16 10 36|50 14 18 66|5c 01 06 12|35 7e 46 0a∥1a 39 6f 17|59 75 48 5d|2a 07 57 39|0f 30 21 30| D₂ is then obtained by substituting D₀ in Eq. (13).

2. According to the disclosed method of the invention, one obtains: 166·P=|52 4b 78 13|0f 5b 57 7b|4f 32 68 32|33 77 4a 18∥51 3d 58 5d|3e 15 7b 59|7e 76 04 31|44 20 16 39| 167·Q=|08 72 67 3c|36 58 65 22|06 42 1c 57|09 62 56 19∥17 49 00 70|63 52 59 40|42 56 64 36|60 7f 4c 5c| 245·D ₁=|70 2f 0f 19|69 17 2a 3f|15 71 72 77|0f 6b 5a 0b∥5c 4d 37 3a|04 32 6a 44|16 27 37 3e|2b 6f 7b 55| Therefore, D ₀=|2a 16 10 36|50 14 18 66|5c 01 06 12|35 7e 46 0a∥1a 39 6f 17|59 75 48 5d|2a 07 57 39|0f 30 21 30| Likewise, D₂ is obtained by substituting D₀ in Eq. (13).

The above example reveals that even though the value of Q obtained by the techniques disclosed in the invention is different from the one computed by the prior art, however, the functions of protecting and recovering the user data are identical to the one in the prior art.

Correctness of the Algorithm and its Mathematical Meaning

Take GF(2⁸) as an example. Suppose Y and X are composed of 8 XOR operation units, each of which has a length of w bits. Here w is an appropriate number, such as 32 in the previous example. Y and X are represented in a vector format as follows,

${Y = \begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ \vdots \\ y_{7} \end{bmatrix}},{X = \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ \vdots \\ x_{7} \end{bmatrix}}$ where y_(i) and x_(i) are w-bit numbers and 0≦i≦7.

Let Y=K·X, where K is a constant whose map table is the matrix M_(K). Then

${y_{i} = {\sum\limits_{j = 0}^{7}\left( {m_{ij} \cdot x_{j}} \right)}},{{{wherein}\mspace{14mu} 0} \leqq i \leqq 7}$ That is,

$y_{0} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j}} \right)}$ $y_{1} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j}} \right)}$ $y_{2} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j}} \right)}$ $y_{3} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j}} \right)}$ $y_{4} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j}} \right)}$ $y_{5} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j}} \right)}$ $y_{6} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j}} \right)}$ $y_{7} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j}} \right)}$

Let y_(i,j) and x_(i,j) denote the j-th bits of y_(i) and x_(i), respectively, where 0≦i≦7 and 0≦j≦w−1. Since both y_(i) and x_(i) have w bits, the above equations can be unfolded as follows:

$\begin{matrix} {{y_{0,0} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,0}} \right)}}{{y_{0,1} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{0,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,{w - 1}}} \right)}}} & (14) \\ {{y_{1,0} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,0}} \right)}}{{y_{1,1} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{1,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,{w - 1}}} \right)}}} & (15) \\ {{y_{2,0} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,0}} \right)}}{{y_{2,1} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{2,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,{w - 1}}} \right)}}} & (16) \\ {{y_{3,0} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,0}} \right)}}{{y_{3,1} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{3,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,{w - 1}}} \right)}}} & (17) \\ {{y_{4,0} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,0}} \right)}}{{y_{4,1} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{4,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,{w - 1}}} \right)}}} & (18) \\ {{y_{5,0} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,0}} \right)}}{{y_{5,1} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{5,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,{w - 1}}} \right)}}} & (19) \\ {{y_{6,0} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,0}} \right)}}{{y_{6,1} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{6,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,{w - 1}}} \right)}}} & (20) \\ {{y_{7,0} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,0}} \right)}}{{y_{7,1} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu}{so}\mspace{14mu}{forth}\mspace{14mu}{until}\mspace{14mu} y_{7,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,{w - 1}}} \right)}}} & (21) \end{matrix}$

Analyzing Eqs. (14) to (21), one finds:

$\begin{bmatrix} y_{0,0} \\ y_{1,0} \\ y_{2,0} \\ \vdots \\ y_{7,0} \end{bmatrix} = {\begin{bmatrix} m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,7} \\ m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,7} \\ m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,7} \\ \vdots & \vdots & \vdots & \; & \vdots \\ m_{7,0} & m_{7,1} & m_{7,2} & \ldots & m_{7,7} \end{bmatrix}_{K} \cdot \begin{bmatrix} x_{0,0} \\ x_{1,0} \\ x_{2,0} \\ \vdots \\ x_{7,0} \end{bmatrix}}$

That is, (y_(0,0) y_(1,0) . . . y_(7,0)) and (x_(0,0) x_(1,0) . . . x_(7,0)) satisfy the definition of the map table in Eq. (9). Therefore, the former one is the product of K and the latter one in the Galois Field. Likewise, the numbers of (y_(0,j) y_(1,j) . . . y_(7,j)) for all j satisfying 0≦j≦w−1 are the products of K and (x_(0,j) x_(1,j) . . . x_(7,1)).

The above-mentioned analysis provides a mathematical meaning for the disclosed technique. Please refer to FIG. 3 and take GF(2⁸) as an example. The Galois Field products obtained according to the invention is equivalent to the results obtained from the following steps:

-   -   1. Read the data sector with a length of (w·8) bits, where w is         an appropriate value as described above.     -   2. In the data sector, start from the i-th bit and pick one bit         every w bits, until it forms a GF(2⁸) number x_(i), wherein         0≦i≦7.     -   3. Obtain •y_(i)=K˜x_(i), wherein 0≦i≦7, using the conventional         techniques.     -   4. Store y_(i) back to the memory address where stores the final         multiplication product. The location of each bit of y_(i) should         move back to the one corresponding to the original location in         x_(i), wherein 0≦i≦7.

From the viewpoint of the “equivalent method” mentioned above, the disclosed method of the invention still follows the algebraic principles of the Galois Field. The difference from the prior art is the way of data sampling. That is, the disclosed method of the invention can be regarded as being equivalent to sampling one bit every w bits in the data sector until a GF(2^(a)) number is obtained.

For example, as shown in FIG. 3, suppose an XOR operation unit has w bits of a data length, and 8 XOR operation units form a multiplication unit. One embodiment of the invention is considered to be equivalent to the multiplication result outlined in the following steps. Step1, pick the first bit of each XOR operation unit to form an 8-bit number (b₀b₁b₂b₃b₄b₅b₆b₇). Multiply K by (b₀b₁b₂b₃b₄b₅b₆b₇) to obtain (b₀′b₁′b₂′b₃′b₄b₅′b₆′b₇′). Then, put each bit of (b₀′b₁′b₂′b₃′b₄′b₅′b₆′b₇′) back to the corresponding location where the original (b₀b₁b₂b₃b₄b₅b₆b₇) comes from. Step2, perform the operation with the same K on the number (c₀c₁c₂c₃c₄c₅c₆c₇) formed by picking the second bit of each XOR operation unit and then obtain (c₀′c₁′c₂′c₃′c₄′c₅′c₆′c₇′). Put each bit of (c₀′c₁′c₂′c₃′c₄′c₅′c₆′c₇′) back to the corresponding location where the original (c₀c₁c₂c₃c₄c₅c₆c₇) comes from. This procedure repeats until all the w·8 bits are computed.

In contrast, the prior art samples data in sequence, as shown in FIG. 4. The product of each byte with K has to be computed one by one. Therefore, it is difficult to enlarge the data amount computed so as to speed up the operation.

From the equivalent point of view mentioned above, although the invention has different sampling method from the prior art, this does not affect the correctness of Eqs. (2) to (8). Therefore, the functions of data protecting and recovering remain the same.

The above-mentioned “equivalent method” is only for explaining the essence of the invention. In practice, the disclosed method of the invention can simultaneously compute several Galois Field products, thereby increasing the operation speed of the RAID system. This advantage originates from the special data sampling method in the “equivalent method”.

System Structure Using the Disclosed Algorithm

In an embodiment of the invention, the disclosed method is applied to a redundant array of independent disk (RAID) subsystem. With reference to FIG. 5, the physical storage device (PSD) array 600 consists of several disk drives. When a host 10 accesses the PSD array 600, the entire PSD array 600 is regarded as a single logic disk drive. The primary objective of a storage virtualization controller (SVC) 100 is to map the combination of all sectors in the disk drives to form a logic disk drive visible to the host 10. After an I/O request sent out from the host 10 is received by the controller 100, the I/O request is first analyzed and interpreted. The related operations and data are then compiled into I/O requests of the disk drives.

In this embodiment, the SVC 100 comprises a host-side I/O device interconnect controller 120, a central processing circuit (CPC) 140, a memory 180, and a device-side I/O device interconnect controller 500. Although these components are described using individual functional blocks, in practice some or even all the functional blocks can be integrated on a single chip.

The host-side I/O device interconnect controller 120 is connected to the host 10 and the CPC 140 to be the interface and buffer between the SVC 100 and the host 10. It receives the I/O requests and the related data transmitted from the host 10 and converts and/or maps them to the CPC 140.

The memory 180 is connected to the CPC 140 to be a buffer. It buffers the data transmitted between the host 10 and the PSD array 600 that pass through the CPC 140.

The device-side I/O device interconnect controller 500 is disposed between the CPC 140 and the PSD array 600 to be the interface and buffer between the SVC 100 and the PSD array 600. The device-side I/O device interconnect controller 500 receives the I/O requests and the related data transmitted from the CPC 140 and maps and/or transmits them to the PSD array 600.

The CPC 140 includes a CPU chipset 144 that has a parity engine 160, a central processing unit (CPU) 142, a read only memory (ROM) 146, and a non-volatile random access memory (NVRAM) 148. The CPU 142 can be, for example, a Power PC CPU. The ROM 146 can be a flash memory for storing the basic input/output system (BIOS) and/or other programs. The CPU 142 is coupled via the CPU chipset 144 to other electronic devices (e.g., the memory 180). The NVRAM 148 is used to store information related to the status of I/O operations on the PSD array 600, so that the information can be used as a check when the power is unexpectedly shut down before the I/O operations are finished. The ROM 146, the NVRAM 148, an LCD module 550, and an enclosure management service (EMS) circuit 560 are coupled to the CPU chipset 144 via an X-bus. Moreover, the NVRAM 148 is optional; namely, it may be omitted in other embodiment. Although the CPU chipset 144 is described as a functional block integrated with the parity engine 160, they can be disposed separately on different chips in practice.

In an embodiment of the invention, the target data processed in the multiplication operations may come from the PSD array 600 or the host 10. The multiplication result may be stored in the memory 180, the disk drives of the PSD 600, or the buffer built in the parity engine 160 or the CPU 142 (not shown in the drawing). The algorithm of the invention is implemented by program coding. The program can be stored in the ROM 146 or the memory 180 for the CPC 140 to execute. In other words, the CPC 140 is responsible for generating map tables corresponding to the numbers in a field domain (e.g., GF(2⁸)) during power on or on line. The generated map tables can be stored in the memory 180. In another embodiment of the invention, all the necessary map tables can be computed in advance and stored in the ROM 146 or the memory 180 so that the CPC 140 only needs to access the stored map tables after power on. During the online real-time operations, for a given multiplication unit, an XOR operation unit is taken as an unit to perform an XOR operation on the target data stored in the memory according to the map tables. The multiplication result is then obtained after several the XOR operations.

Although in the above embodiment, disks are taken as an example for the physical storage devices (PSDs) used in the RAID subsystem, it is noted that other kinds of physical storage devices, such as CD, DVD, etc., can be used alternatively, depending on different demands of the market.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims. 

What is claimed is:
 1. A method for accessing data in a physical storage device (PSD) array including a plurality of PSDs, at least one memory, a storage virtualization controller (SVC) comprising a central processing circuit (CPC), and a hardware computation device, comprising the steps of: receiving a first I/O request from a host by the SVC for writing data into a first user data block in the PSDs of the PSD array, said first user data block being located on a first stripe having a first parity data block and a second parity data block; updating the second parity data block due to the first I/O request writing data into the first user data block, comprising the steps of: using at least one memory for temporarily storing a first group of target data sets provided by a data source, wherein each of the first group of target data sets is of a length of a multiplication unit containing “a” XOR operation units, each of the XOR operation units being of a data length of “w” bits and being used for performing an XOR operation, and the multiplication unit being of a data length of “a” multiplying “w” bits and being used for performing a multiplication operation, wherein “a” and “w” are each a positive integer larger than one and “w” is independent of “a”; using the central processing circuit (CPC) to generate or to access at least one map table each associated with one value in a field, and storing the at least one map table in the at least one memory, wherein said at least one map table has a dimension of “a” by “a”; performing a multiplication operation on a first target data set of the first group of target data sets to obtain a first multiplication result, wherein said performing a multiplication operation is through using the hardware computation device to perform a plurality of XOR operations on the first target data set according to the at least one map table, wherein each of the plurality of XOR operations is performed on a part of the first target data set, said part of the first target data set being data in one of the “a” XOR operation units; storing the first multiplication result in the at least one memory; generating the second parity data block by obtaining a plurality of multiplication results by performing a plurality of multiplication operations each of which comprising performing a plurality of XOR operations on its corresponding target data set of the first group of target data sets; and storing the generated second parity data set; and returning by the SVC a completion message of the first I/O request to the host.
 2. The method of claim 1, further comprising the steps of: receiving a second I/O request from the host by the SVC for reading data from a plurality of user data blocks in the PSDs of the PSD array, said user data blocks being located on the first stripe; identifying by the SVC data access errors on two of the user data blocks of the first stripe; initializing by the SVC a recovering process involving the second parity data block to recover a failed-access user data block, wherein the recovering process comprises the steps of: using at least one memory for temporarily storing a second group of target data sets provided by a data source, wherein each of the second group of target data sets is of a length of a multiplication unit containing “a” XOR operation units, each of the XOR operation units being of a data length of “w” bits and being used for performing an XOR operation, and the multiplication unit being of a data length of “a” multiplying “w” bits and being used for performing a multiplication operation, wherein “a” and “w” are each a positive integer larger than one and “w” is independent of “a”; performing a multiplication operation on a second target data set of the second group of target data sets to obtain a second multiplication result, wherein said performing a multiplication operation is through using the hardware computation device to perform a plurality of XOR operations on the second target data set according to the at least one map table, wherein each of the plurality of XOR operations is performed on a part of the second target data set, said part of the second target data set being data in one of the “a” XOR operation units; storing the second multiplication result in the at least one memory; and generating a data set identical to the failed-access user data block by obtaining a plurality of multiplication results by performing a plurality of multiplication operations each of which comprising performing a plurality of XOR operations on its corresponding target data set of the second group of target data sets; and returning by the SVC the regenerated data set identical to the failed-access user data block to the host.
 3. The method of claim 2, wherein the regenerated data set is obtained using the following formula: D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy)) D _(y)=(P+P _(xy))+D _(x) where x and y are the serial numbers of two user data PSDs with errors of the plurality of PSDs; D_(x) and D_(y) are target data sets corresponding to the two user data PSDs x and y of the plurality of PSDs; A and B are constants only dependent upon x and y: A=g ^(y-x)·(g ^(y-x)+1)⁻¹ B=g ^(−x)·(g ^(y-x)+1)⁻¹ P_(xy) and Q_(xy) are the values of P and Q, respectively, when D_(x) and D_(y) are both 0, i.e., P _(xy) +D _(x) +D _(y) =P Q _(xy) +g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q where “+” represents an XOR operation; and “·” represents the multiplication operation of the Galois Field.
 4. The method of claim 1, wherein the second parity block is obtained using the following formula: Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . +g ^(n-1) ·D _(n-1) where g is a generator of a Galois Field and given to be 2; D₀, D₁, D₂, . . . , D_(n-1) denote target data sets from n number of user data PSDs of the plurality of PSDs, respectively; “+” represents an XOR operation; and “·” represents the multiplication operation of the Galois Field.
 5. The method of claim 1, wherein the field is a Galois Field and wherein the map table is generated according to an algorithmic rule of the Galois Field.
 6. The method of claim 5, wherein when the domain of the Galois Field is GF(2⁸) the algorithmic rule is: m′ _(0,j) =m _(7,j),0≦j≦7 m′ _(1,j) =m _(0,j),0≦j≦7 m′ _(2,j) =m _(1,j) +m _(7,j),0≦j≦7 m′ _(3,j) =m _(2,j) +m _(7,j),0≦j≦7 m′ _(4,j) =m _(3,j) +m _(7,j),0≦j≦7 m′ _(5,j) =m _(4,j),0≦j≦7 m′ _(6,j) =m _(5,j),0≦j≦7 m′ _(7,j) =m _(6,j),0≦j≦7 where m_(0,j)˜m_(7,j) and m′_(0,j)˜m′_(7,j) with 0≦j≦7 are elements of matrixes M_(K) and M_(K′), respectively, M_(K) being a given matrix associated with K, M_(K′) being a matrix associated with K′=2·K wherein K≠0.
 7. The method of claim 1, wherein the plurality of XOR operations are performed according to the following formula: $Y = {\begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ \vdots \\ y_{a - 1} \end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix} m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,{a - 1}} \\ m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,{a - 1}} \\ m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,{a - 1}} \\ \vdots & \vdots & \vdots & \; & \vdots \\ m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},{a - 1}} \end{bmatrix}_{K} \cdot \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ \vdots \\ x_{a - 1} \end{bmatrix}}}}$ namely $y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{ij} \cdot x_{j}} \right)}$ where M_(K) is a matrix representing the map table associated with K; m_(i,j) represent elements in the matrix M_(K) with 0≦i, j≦a−1, and m _(i,j) ·x _(j) =x _(j), if m _(i,j)=1 m _(i,j) ·x _(j)=0, if m _(i,j)=0 where x₀, x₁, x₂, . . . , and x_(a-1) represent data whose length is the same as the length of the XOR operation unit, respectively, X represents data of the multiplication unit; and Y represents the result of multiplying K by X.
 8. The method of claim 7, wherein the XOR operation performed according to the map tables is the one selecting the data of the XOR operation unit whose corresponding elements in the same row of the matrix M are 1 to do the XOR operation.
 9. The method of claim 1, wherein the length of the XOR operation unit is determined according to a processing unit of a central processing unit (CPU) or the hardware computation device.
 10. The method of claim 1, wherein the length of the XOR operation unit is 32 bits or 64 bits.
 11. The method of claim 1, wherein the length of the multiplication unit is 32 bytes or 64 bytes.
 12. The method of claim 1, wherein the data source is a physical storage device (PSD) array or a computer host.
 13. A controller for accessing data in a physical storage device (PSD) array including a plurality of PSDs and a hardware computation device, comprising: at least one I/O device interconnect controller for receiving a first I/O request from a host for writing data into a first user data block in the PSDs of the PSD array, said first user data block being located on a first stripe having a first parity data block and a second parity data block; at least one memory for temporarily storing a first group of target data sets provided by a data source, wherein each of the first group of target data sets is of a length of a multiplication unit containing “a” XOR operation units, each of the XOR operation units being of a data length of “w” bits and being used for performing an XOR operation, and the multiplication unit being of a data length of “a” multiplying “w” bits and being used for performing a multiplication operation, wherein “a” and “w” are each a positive integer larger than one and “w” is independent of “a”; and a central processing circuit (CPC) for interacting with the at least one memory, for generating or accessing at least one map table each associated with one value in a field, and storing the at least one map table in the at least one memory, wherein the at least one map table has a dimension of “a” by “a”; wherein the CPC is for performing a multiplication operation on a first target data set of the first group of target data sets to obtain a first multiplication result, wherein said performing a multiplication operation is through using the hardware computation device to perform a plurality of XOR operations on the first target data set according to the at least one map table, wherein each of the plurality of XOR operations is performed on a part of the first target data set, said part of the first target data set being data in one of the “a” XOR operation units; wherein the first multiplication result is stored in the at least one memory; wherein the CPC is further for generating the second parity data block for storing into the first stripe of the PSD array by obtaining a plurality of multiplication results by performing a plurality of multiplication operations each of which comprising performing a plurality of XOR operations on its corresponding target data set of the first group of target data sets.
 14. The controller of claim 13, wherein the CPC further includes a CPU.
 15. The controller of claim 13, wherein the data source is a PSD array or a computer host for providing the first group of target data sets for the multiplication operation.
 16. The controller of claim 13 further comprising a device-side I/O device interconnect controller connected between the PSD array and the CPC.
 17. The controller of claim 13 further comprising a host-side I/O device interconnect controller connected between the host and the CPC.
 18. The controller of claim 13, wherein the field is a Galois Field and the map table is generated according to an algorithmic rule of the Galois Field.
 19. The controller of claim 18, wherein when the domain of the Galois Field is GF(2⁸), the algorithmic rule is: m′ _(0,j) =m _(7,j),0≦j≦7 m′ _(1,j) =m _(0,j),0≦j≦7 m′ _(2,j) =m _(1,j) +m _(7,j),0≦j≦7 m′ _(3,j) =m _(2,j) +m _(7,j),0≦j≦7 m′ _(4,j) =m _(3,j) +m _(7,j),0≦j≦7 m′ _(5,j) =m _(4,j),0≦j≦7 m′ _(6,j) =m _(5,j),0≦j≦7 m′ _(7,j) =m _(6,j),0≦j≦7 where m_(0,j)˜m_(7,j) and m′_(0,j)˜m′_(7,j) with 0≦j≦7 are elements of matrixes M_(K) and M_(K′), respectively, M_(K) being a given matrix associated with K, M_(K′) being a matrix associated with K′=2·K wherein K≠0.
 20. The controller of claim 13, wherein the the plurality of XOR operations are performed according to the following formula: $Y = {\begin{bmatrix} y_{0} \\ y_{1} \\ y_{2} \\ \vdots \\ y_{a - 1} \end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix} m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,{a - 1}} \\ m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,{a - 1}} \\ m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,{a - 1}} \\ \vdots & \vdots & \vdots & \; & \vdots \\ m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},{a - 1}} \end{bmatrix}_{K} \cdot \begin{bmatrix} x_{0} \\ x_{1} \\ x_{2} \\ \vdots \\ x_{a - 1} \end{bmatrix}}}}$ namely, $y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{ij} \cdot x_{j}} \right)}$ where M_(K) is a matrix representing the map table associated with K; m_(i,j) represent elements in the matrix M_(K) with 0≦i, j≦a−1, and m _(i,j) ·x _(j) =x _(j), if m _(i,j)=1 m _(i,j) ·x _(j)=0, if m _(i,j)=0 where x₀, x₁, x₂, . . . , and x_(a-1) represent data whose length is the same as the length of the XOR operation unit, respectively, X represents data of the multiplication unit; and Y represents the result of multiplying K by X.
 21. The controller of claim 13, wherein the length of the XOR operation unit is determined according to a processing unit of the central processing unit (CPU) or the hardware computation device.
 22. The controller of claim 13, wherein the length of the XOR operation unit is 32 bits or 64 bits.
 23. The controller of claim 13, wherein the length of the multiplication unit is 32 bytes or 64 bytes. 